This section provides an overview of the
Raspberry Pi hardware and firmware. The initial few sections don't assume any
significant knowledge about hardware or software. They were essentially
just my personal notes on figuring out what device I was looking at.
However, the sections will become increasingly more technical as we
progress but I will endeavor to explain things as I go.
Note: This annex is dated and reflects the very first model of Pi that came out. Many of the statements here may not reflect later models.
Model/Revision am I working with?" It's always good to know what
you're holding in your hand. However, I found that it wasn't entirely clear
from the markings on the board what model and/or revision it was. Indeed,
there appears to be several types of "Revision" number. One has
to do with the PCB specs, there's one that seems to identify the manufacturer,
and there's one that is related to the CPU.
Fortunately, other people have had some issues with figuring out their hardware
and they have been kind enough to document their findings in a number of
places. One of these places is elinux.org
which has three pages that are very helpful - one that gives a complete hardware breakdown, one that
deals with the board history,
andone that provides other
specific hardware details.
First, let's take a hardware tour of the device. The figure below shows
the non-obvious parts of the Pi.
Figure 38: Raspberry Pi Quick Overview
My board has the following devices:
Memory: Samsung 313 K4P4G324EB-AGC1 (512MB RAM chip)
USB Chip: SMSC LAN9513-JZX
RG2: 17-336 (RQB44)
C6: 220 CFP 20N
I couldn't find an exact match on the hardware details page. I
noticed that some of the numbers had "8" where there should be
To find the
board revision, the board history page suggests using a command-line prompt to
query cpuinfo. This assumes that you have been able to get the Pi up and
running with an operating system. If you haven't, there is plenty of info
on getting this done all over the web. I would suggest using either of
Note that when you first bootfrom the flash card, it will ask which
distro you want to install. I Googled each to see what they were
about although there is a short description attached at the NOOBS site.
Once you have Raspbian up and running, you can "open a prompt" and
find out which board revision you have. Double-click on the LXTerminal
icon (shown in the figure below circled in white).
Figure 39: LX Terminal on Pi
You will see a new window similar to the one shown below.
Figure 40: LX Terminal Open
Now you can
use the keyboard to enter a command to report information about your Pi.
Type in the instruction shown below:
produces a list of information as shown in the figure below.
Figure 41: CPU Info
bits are Hardware and Revision. The information shown above is
not representative of a real board because the screen-captures are from a Pi
simulator in Qemu. However, my board reports the following:
Therefore, according to the table above, I am working with a Model B, Revision
2.0 board made by Sony (with 512MB RAM).
A Closer Look at the Pi Hardware
Because the Pi has a large following, there
is plenty of good information available on many websites to help us out.
This is particularly of value given that there are sections of the Pi
that are not available for us to scrutinize. These are proprietary and,
to know about them, you need to sign a Non-Disclosure Agreement. That's
In conducting this closer look, I have searched far and wide on the Internet.
I am in debt to a number of individuals who have put their explorations
out there for me to stumble upon. These include:
- David Welch
- This is the defacto location for everything low-level.
The BMC2835 System on a Chip (SoC)
The core of
the Raspberry Pi is the Broadcom 2835 System-on-a-Chip. If you look
carefully for it on the board, you might be surprised to find that you can't
find it. The figure below (from wikipedia) shows the SoC chip squarely
in the middle of the board but if you inspect your board, you'll see that the
chip there is a Samsung memory device. So what's going on?
Figure 42: : RaspBerry Pi Board (Courtesy: http://en.wikipedia.org/wiki/File:Raspberrypi_pcb_overview_v04.svg)
chip is mounted on top of the SoC chip as shown in the figure below. This
is a common practice for mobile devices where memory is concerned.
Figure 43: Ball Grid Arry Mounting of Memory
chip is put on top of the SoC using a Ball Grid Array (BGA). Wikipedia
has a pretty good description of what that means electrically and mechanically.
For us, the only thing that matters is that we now know where the CPU is
located on the board.
I did quite a bit of digging to find out the hardware details of this device.
However, it appears that SoC vendors live in a very competitive world and seem
reluctant to give away details about the innards of their chips. Visit a
number of locations around the web while searching for Broadcom specs and
you'll see what I mean. Of course, that just makes the task of working at the
hardware layer that much more challenging (in a positive way). [UPDATE:
Broadcom has since made their innards open source under a 3-clause BSD license http://www.raspberrypi.org/archives/6299)
the Broadcom website:
The BCM2835 is a cost-optimized, full HD, multimedia applications
processor for advanced mobile and embedded applications that require the
highest levels of multimedia performance. Designed and optimized for power
efficiency, BCM2835 uses Broadcom's VideoCore®
IV technology to enable applications in media playback, imaging, camcorder,
streaming media, graphics and 3D gaming.
What that means is that our little Raspberry Pi is optimized for multimedia.
Using the available sources from around the web, here is what I know of the
- The device
contains two main processing units: an ARM1176JZF-S processor and Broadcom
VideoCore Graphics Processing Unit (GPU).
- My device
contains 512 MB of DRAM.
- The BCM2853
contains a number of peripherals as indicated in an interface manual
[BCM1]. These peripherals are accessible to the ARM processor and include:
Purpose Input/Output (GPIO)
Serial Bus (USB)
- Direct Memory
Access (DMA) controller
Circuit (I2C) master
- Pulse Width
schematics are usually the most desirable thing to have since they represent
ground truth. Schematics are available from the Pi website.
However, because schematics can be a bit daunting at first, I present
aless detailed block diagram of the Pi in Figure 44 showing essential features within
the SoC connected to devices on the Pi board.
Figure 44: Broadcom SoC Block Diagram
header connectors P1 and P5 give us access to some of the peripherals on the
SoC. However, as illustrated in Figure 44, some of those GPIO pins are
"dual purpose". Figure 45 shows how each pin can be either a GPIO or can belong to one of the
special peripherals of the SoC (i.e. I2C, UART). The actual function of
each GPIO pin is configured by the software we write after the SoC boots up.
Figure 45: I/O Configuration
Ground and Power Pins
are marked "Ground", "5V Power", and "3V3 Power".
These pins, as you might have guessed, provide power and ground reference
signals. If you connect any sort of circuit to any of the pins on the
GPIO header, the ground reference of your circuit must be connected to one
of the ground pins on the GPIO header. If you do not do this, the
circuit you attach may not understand signal voltages the same way that the Pi
Purpose Input Output (GPIO) pin is an electrical interface that can be
configured to do a number of different things. It can act as a digital
input (i.e. accepts signals that are either 0V or 5V) or a digital output.
They can also be configured to act as analog inputs and outputs (they can
interpret and convert voltages on the pin between 0V and 5V into numbers and
vice-versa). They can also be configured to do special functions such as
being part of a serial port. We shall see some of these later.
According to the BCM 2835 ARM Peripherals manual, there are 54 general purpose
I/O pins. Configuring each pin to do different things is achieved by
writing data into one or more of the GPI0 configuration registers.
There are 41 of these configuration registers as outlined in Chapter 6 of
the Peripherals manual [BCM1]. We shall briefly cover a few of these
General Purpose Function Select (GPFSEL) Registers
There are 6 registers named GPFNSEL0 - GPFNSEL5. Each of these thirty-two
bit registers is divided up into 10 groups of three bits (the final two bits
are not used). Each three-bit-group determines what each respective pin
does as follows:
The pin is an input
The pin is an output
The pin does alternate function 0
The pin does alternate function 1
The pin does alternate function 2
The pin does alternate function 3
The pin does alternate function 4
The pin does alternate function 5
Example: GPFNSEL0 is used to define what the first 10 GPIO pins do (GPIO0
- GPIO9) as shown in Figure 46.
Figure 46: GPFNSEL0 Register
"alternate functions" that are possible are defined in Chapter 6.2 of
[BCM1]. These are shown in Figure 47. Every pin on each of the P1 and P5 headers is capable of
alternate functions but most pins are not capable of doing every alternate
function. If you plan on using an alternate function, it is important to
know whether all of the pins that are necessary are accessible on the
headers. For example, all but one of the pins for SD1 (GPIO 22-27) are
available on the P1 header (GPIO 26 is not available).
Figure 47: Alternate Function Mapping
General Purpose Output Set n (GPSET) and Clear n (GPCLR)
If you define a GPIO to be a digital output pin, then you need a way of
changing the value of the output pin from logic 0 (zero volts on the pin) to
logic 1 (5 volts on the pin). In many types of CPU, this can be done by
writing a 0 or a 1 to a register the controls the GPIO and the output pin will
just mirror the value found in the register. >
With the Raspberry Pi, this does not appear to be the case. Rather,
setting a GPIO to output a logic 1 (5 volts) is done by writing to one register
while setting the same GPIO to output a logic 0 (0 volts) is done by writing to
a different register.
The registers GPSET0 and GPSET1 are used to set a GPIO to logic 1 (5
volts output). Since each register is 32 bits and there are 54 GPIO, a
minimum of two registers are needed in order to cover every GPIO.
Figure 48: GPSET and GPCLR Registers
There is a second pair of register GPCLR0 and GPCLR1, set up in exactly the
same way, that are used to clear (set to logic 0) each GPIO.
Let's say we want to set GPIO 14 to logic 1, wait a bit, and then clear it to
logic 0. First, we would use a bit-set instruction to cause the bit
corresponding to GPIO 14 in the GPSET0 register to be set to 1.
Then, we wait....
Later we would use a bit-set instruction to cause bit 14 of GPCLR to be set to
Note how, in the second operation, we didn't write a zero to the register but
rather a 1. Putting a 1 in the GPCLR register causes the associated
bit to clear.
General Purpose Pin Level (GPLEV) Registers
Regardless of whether the GPIO is an input or an output, the two registers
GPLEV0 and GPLEV1 can be used to read determine what state they are in (that
is, logic 0 or logic 1). Once again, each bit corresponds to an
individual GPIO so that a minimum of two registers is needed to cover all
General Purpose Event Detected Status (GPEDS) Registers
The registers GPEDS0 and GPEDS1 can be read to determine if a predefined event
has occured on a GPIO. A zero indicates that nothing has happened and 1
indicates that an event has occured. Once again, each bit corresponds to
an individual GPIO so that a minimum of two registers is needed to cover all
There are two types of event:
- The signal on a GPIO goes from 0 to 1 or from 1 to 0 (an edge transition).
- The level on a GPIO is detected to be a zero or a 1.
The type of event that is associated with each GPIO is configured with
registers that will be discussed shortly.
General Purpose Rising Edge Detect Enable (GPREN) Registers
There are two General Purpose Rising Edge Detect Enable registers - GPREN0 and
GPREN1. Each bit corresponds to one of the 54 GPIOs.
Let's say you attachGPIO 5 to a signal on an external circuit and you
want to be notified whenever the signal goes from low to high (0 to 1, zero
volts to five volts). You would set bit 5 of GPREN0 to 1 and then
watch bit 5 of GPEDS0. Whenever that bit becomes 1, then you know that
the signal has transitioned.
Other GPIO Detect Function Enable Registers
There are a pair of registers associated with each of thefollowing events
that can be detected on a GPIO:
- Falling Edge Detect Enable (GPFEN);
- High Detect Enable (GPHEN);
- Low Detect Enable (GPLEN);
- Asyncrhonous Rising Edge Detect Enable (GPAREN); and
- Asynchronous Falling Edge Detect Enable (GPAFEN).
The asynchronous edge detection functions are different from the rising and
falling edge detection in that they are not tied to the system clock.
That is, the rising and falling edge detection is performed at the
beginning of specific clock cycles whereas the asynchronous detections occur
regardless of the clock.
A pull-up or pull-down resistor can be added to an output pin in order to force
it into either a high (5V) or low (0V) state when it is not otherwise being
pulled into either of those states by an external circuit.
GPIO Communications Protocols
As shown in Figure 45, several GPIO pins can be grouped
together and assigned alternate functions. All of these functions are essentially
communications protocols. I describe each of them very briefly
below. They are each fairly well covered on Wikipedia.
I2C - Inter-Integrated Circuit bus: A two wire computer bus
protocol specified originally by Phillips for low speed communications
between devices on a circuit board or between circuits that are close to each
other. I2C requires two bidirectional wires - one for clock
synchronization (SCL) and one for serial data movement (SDA).
SPI - Serial Peripheral Interface bus: This is a four wire serial
bus that includes a synchronization clock signal (SCLK), two data exchange
wires (MOSI and MISO) and a device select signal (SS).
>UART - Universal Asynchronous Receiver Transmitter: A UART
implements the serial protocol that used to be associated with the serial port
on the back of older computers. Most of the computers shipping nowadays
have neither parallel nor serial port connectors anymore. The key
difference between a UART and SPI, I2C, and USB is that there is no shared
clock signal (the interface is asynchronous).
GPIO Register MAP
totally straightforward... What is the specific address to be used when
accessing a register? Pages 5 and 6 of the ARM Peripheral Reference
Manual are somewhat confusing. However, on page 6, it does say the
addresses range from 0x20000000 to 0x20FFFFFF for peripherals. The bus
addresses for peripherals are set up to map onto the peripheral bus address
range starting at 0x7E000000. Thus a peripheral advertised here at bus address
0x7Ennnnnn is available at physical address 0x20nnnnnn.”
Therefore, to arrive at the location in memory to be used during assembly
language programming, take the address presented as part of the manual, remove
7E and insert 20.
What is often done in code segments is to define the base address for all
peripherals and then define base increments for each type of peripheral.
Thus, we can define:
BCM_Peripheral_Base = 0x20000000
GPIO_Base = BCM_Peripheral_Base + 0x200000
PWM_Base = BCM_Peripheral_Base + 0x20C000
CLOCK_Base = BCM_Peripheral_Base + 0x101000
The base address for each of the other peripherals listed above can be found by
scouring the Peripheral Reference Manual. The full memory map for the GPIO is found
on page 90 of the reference manual.
The Pi Boot Process
In this section, I take a closer look at
the boot process.
The Short Answer
In order to have the Pi execute your code
at boot time, the only thing you must really do is ensure that the file kernel.img
exists on the FAT16 partition of the SDCard. In addition, that image file
must begin at address 8000h. That's about it.
The Long Answer
The Broadcom chip is a proprietary affair.
Unlike other CPUs, the ARM is not at the center of the boot process when
power is turned on. Rather, it is the VideoCore GPU.
There are a number of good resources that explain the detailed steps in going
from power-on to executing code at address 8000h by the ARM. Indeed, one
of the easiest to follow is a video by Steve Halladay.
Essentially, the Pi boot process goes as follows:
- When power is
applied, the GPU comes on and suppresses the ARM processor by putting into
a reset state.
- A section of
ROM in the GPU loads the file bootcode.bin into L2 cache and begins
- This code
enables the Pi's SDRAM and then loads start.elf (the GPU's
firmware) into it.
reads config.txt and cmdline.txt for configuration options.
- kernel.img into SDRAM.
Again, we note that bootcode.bin and
start.elf are proprietary code.